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low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 8533-11 revision e 7/9/15 1 ?2015 integrated device technology, inc. g eneral d escription the 8533-11 is a low skew, high performance 1-to-4 crystal oscillator/differential-to-3.3v lvpecl fanout buffer. the 8533- 11 has selectable differential clock or crystal inputs. the clk, nclk pair can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the 8533-11 ideal for those applications demanding well de ned performance and repeatability. f eatures ? 4 differential 3.3v lvpecl outputs ? selectable differential clk, nclk or crystal inputs ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 650mhz ? translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclk input ? output skew: 30ps (maximum) ? part-to-part skew: 150ps (maximum) ? propagation delay: 2ns (maximum) ? 3.3v operating supply ? 0? to 70? ambient operating temperature ? industrial temperature information available upon request ? lead-free package fully rohs compliant b lock d iagram p in a ssignment 8533-11 20-lead tssop 6.5mm x 4.4mm x 0.92 package body g package top view clk nclk xtal1 xtal2 q0nq0 q1 nq1 q2 nq2 q3 nq3 01 clk_en clk_sel d q le
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 2 revision e 7/9/15 t able 1. p in d escriptions t able 2. p in c haracteristics number name type description 1v ee power negative supply pin. 2 clk_en input pullup synchronizing clock enable. when high, clock outputs follows clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when low, selects clk, nclk input. when high, selects xtal input. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6 xtal1 input pulldown crystal oscillator input. 7 xtal2 input pullup crystal oscillator input. 8, 9 nc unused no connect. 10, 13, 18 v cc power positive supply pins. 11, 12 nq3, q3 output differential clock outputs. lvpecl interface levels. 14, 15 nq2, q2 output differential clock outputs. lvpecl interface levels. 16, 17 nq1, q1 output differential clock outputs. lvpecl interface levels. 19, 20 nq0, q0 output differential clock outputs. lvpecl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k
revision e 7/9/15 8533-11 data sheet 3 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able inputs outputs clk_en clk_sel selected source q0:q3 nq0:nq3 0 0 clk, nclk disabled; low disabled; high 0 1 xtal1, xtal2 disabled; low disabled; high 1 0 clk, nclk enabled enabled 1 1 xtal1, xtal2 enabled enabled after clk_en switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or crystal oscillator edge as shown in figure 1 . in the active mode, the state of the outputs are a function of the clk, nclk and xtal1, xtal2 inputs as described in table 3b. inputs outputs input to output mode polarity clk nclk q0:q3 nq0:nq3 0 1 low high differential to differential non inverting 1 0 high low differential to differential non inverting 0 biased; note 1 low high single ended to differential non inverting 1 biased; note 1 high low single ended to differential non inverting biased; note 1 0 high low single ended to differential inverting biased; note 1 1 low high single ended to differential inverting note 1: please refer to the application information section, ?iring the differential input to accept single ended levels? f igure 1. clk_en t iming d iagram
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 4 revision e 7/9/15 t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? t able 4c. d ifferential dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v i ee power supply current 50 ma symbol parameter test conditions minimum typical maximum units i ih input high current nclk v cc = v in = 3.465v 5 ? clk v cc = v in = 3.465v 150 ? i il input low current nclk v cc = 3.465v, v in = 0v -150 ? clk v cc = 3.465v, v in = 0v -5 ? v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc - 0.85 v note1: for single ended applications the maximum input voltage for clk and nclk is v cc + 0.3v. note 2: common mode voltage is de ned as v ih . symbol parameter test conditions minimum typical maximum units v ih input high voltage clk_en, clk_sel 2v cc + 0.3 v v il input low voltage clk_en, clk_sel -0.3 0.8 v i ih input high current clk_en v in = v cc = 3.465v 5 ? clk_sel v in = v cc = 3.465v 150 ? i il input low current clk_en v in = 0v, v cc = 3.465v -150 ? clk_sel v in = 0v, v cc = 3.465v -5 ? a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70?
revision e 7/9/15 8533-11 data sheet 5 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer t able 4d. lvpecl dc c haracteristics , v cc = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc - 1.4 v cc - 1.0 v v ol output low voltage; note 1 v cc - 2.0 v cc - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: outputs terminated with 50 to v cc - 2v. t able 5. c rystal c haracteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 14 25 mhz equivalent series resistance (esr) 50 shunt capacitance 7p f t able 6. ac c haracteristics , v cc = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units f max output frequency 650 mhz t pd propagation delay; note 1 ? 650mhz 1.0 2.0 ns tsk(o) output skew; note 2, 5 30 ps tsk(pp) part-to-part skew; note 3, 5 150 ps t r / t f output rise/fall time 20% to 80% @ 50mhz 300 700 ps odc output duty cycle; note 4 47 50 53 % all parameters measured at 500mhz unless noted otherwise. the cycle-to-cycle jitter on the input will equal the jitter on the output. the part does not add jitter. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 4: measured using clk. for xtal input, refer to application note. note 5: this parameter is de ned in accordance with jedec standard 65.
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 6 revision e 7/9/15 p arameter m easurement i nformation p ropagation d elay d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod o utput s kew
revision e 7/9/15 8533-11 data sheet 7 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer a pplication i nformation the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 2. s ingle e nded s ignal d riving d ifferential i nput f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r11k c10.1u r2 1k single ended clock input clknclk vcc
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 8 revision e 7/9/15 f igure 4c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r150 r350 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clknclk 3.3v input r250 zo = 50 ohm input hiperclocks clknclk 3.3v r3125 r284 zo = 50 ohm 3.3v r4125 lvpecl r184 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 4a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to con rm the driver termination requirements. for example in figure 4a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r250 input lvhstl driver icshiperclocks r150 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clknclk zo = 50 ohm r1100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v f igure 4e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3125 hiperclocks clknclk 3.3v r5100 - 200 3.3v r284 3.3v r6100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r184 r4125 c2 lvpecl c1
revision e 7/9/15 8533-11 data sheet 9 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer s chematic e xample figure 6 shows a schematic example of the 8533-11. in this example, the xtal input is selected. the decoupling capacitors should be physically located near the power pin. for 8533-11, the unused clock outputs can be left oating. f igure 6. 8533-11 lvpecl b uffer s chematic e xample x1 c3 0.1u r950 r850 u1 ics8533-11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 vee clk_en clk_sel clk nclk xta l 1 xta l 2 nc nc vcc nq3 q3 vcc nq2 q2 nq1 q0 nq0 vcc q1 r250 3.3v r12 1k 3.3v 3.3v c2 0.1u +- 3.3v zo = 50 zo = 50 r11 1k r150 zo = 50 zo = 50 c4 40p - 60pf r350 c1 0.1u r750 +- c5 spare 3.3v c rystal i nput i nterface a crystal can be characterized for either series or parallel mode operation. the 8533-11 fanout buffer has a built-in crystal oscillator circuit. this interface can accept either a series or parallel crystal without additional components as shown in figure 5. the physical location of the crystal should be located as close as possible to the xtal1 and xtal2 pins. the experiments show that using a 19.44mhz crystal results in an output frequency of 19.4404746mhz and approximately 44% of duty cycle. c140p xta l 2 xta l 1 c2 spare x1 cry stal f igure 5. c rystal i nput i nterface
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 10 revision e 7/9/15 p ower c onsiderations this section provides information on power dissipation and junction temperature for the 8533-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8533-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 50ma = 173.3mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 30.2mw = 120.8mw total power _max (3.465v, with all outputs switching) = 173.3mw + 120.8mw = 294.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125?. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6?/w per table 7 below. therefore, tj for an ambient temperature of 70? with all outputs switching is: 70? + 0.294w * 66.6?/w = 89.58?. this is well below the limit of 125?. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ow, and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7. t hermal r esistance ja for 20- pin tssop, f orced c onvection
revision e 7/9/15 8533-11 data sheet 11 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max - v oh_max ) = 1.0v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ?(v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1v)/50 ] * 1v = 20.0mw pd_l = [(v ol_max ?(v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 7. lvpecl d river c ircuit and t ermination
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 12 revision e 7/9/15 r eliability i nformation t ransistor c ount the transistor count for 8533-11 is: 428 t able 8. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
revision e 7/9/15 8533-11 data sheet 13 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer p ackage o utline - g s uffix for 20 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, ms-153 symbol millimeters min max n2 0 a -- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa -- 0.10
low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer 8533-11 data sheet 14 revision e 7/9/15 t able 10. o rdering i nformation part/order number marking package shipping package temperature 8533ag-11lf ics8533ag11l 20 lead ?ead-free tssop tube 0? to 70? 8533AG-11LFT ics8533ag11l 20 lead ?ead-free tssop tape and reel 0? to 70?
revision e 7/9/15 8533-11 data sheet 15 low skew, 1-to-4, crystal oscillator/ differential-to-3.3v lvpecl fanout buffer revision history sheet rev table page description of change date d 3 revised figure 1, clk_en timing diagram. 10/18/01 d 3 revised figure 1, clk_en timing diagram. 11/2/01 d 8-10 deleted crystal oscillator circuit frequency fine tuning section from datasheet. 12/11/01 dt 5 5 shortened crystal characteristics table. esr row, values have changed from 50 min, 80 max. to 70 max. 1/11/02 d 8 added termination for lvpecl outputs section. 5/28/02 d 6 output load test circuit diagram - corrected v ee equation to read, v ee = -1.3v ?0.165v from v ee = -1.3v ?0.135v. 10/3/02 e t2 t4b t4d t5 24 4 5 5 5 7 7 8 9 9 pin characteristics table - changed c in from 4pf max. to 4pf typical. absolute maximum ratings - revised output rating. lvcmos dc characteristics table - changed v ih max. from 3.765v to v cc + 0.3v. lvpecl dc characteristics table - changed v swing max. from 0.85v to 1.0v. crystal characteristics table - changed esr from 70 max. to 50 max. ac characteristics table - deleted osctol row from table. updated single ended signal driving differential input diagram. updated lvpecl output termination diagrams. added differential clock input interface section. added crystal section. added schematic example. 10/30/03 e t10 1 14 features section - added lead-free bullet. ordering information table - added ?ead-free part number. 12/14/04 e t10 14 ordering information table - removed leaded devices. updated data sheet format. 7/9/15
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